The Industrial Mathematics KTN has released a new report on The GPU Computing Revolution: from Multi-Core CPUs to Many-Core Graphics Processors. Written for a nonspecialist audience, it explains the background to technology developments that are changing the face of computing, and shows what business and government can do to exploit the resulting opportunities. The GPU Computing Revolution has been produced in collaboration with the London Mathematical Society and written by Simon McIntosh-Smith of the University of Bristol.
View the full report (1.3MB) by clicking this link.
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Computer architectures are undergoing their most radical change in a decade. In the past, processor performance has been improved largely by increasing clock speed: the faster the clock speed, the faster a processor can execute instructions, and thus the greater the performance that is delivered to the end user. This drive to greater and greater clock speeds has stopped, and indeed in some cases is actually reversing. Instead, computer architects are designing processors that include multiple cores that run in parallel. For the purposes of this report we shall think of a core as one independent 'brain', able to execute its own stream of instructions, independently fetching the data it requires and writing its own results back to a main memory. This shift from increasing clock speeds to increasing core counts - and thus increasing parallelism - is presenting significant new opportunities and challenges.
During this architectural shift a new class of many-core computer architectures is emerging from the graphics market into the mainstream. This new class of processor already exploits hundreds or even thousands of cores. Many-core processors potentially offer an order of magnitude greater performance than conventional processors, a significant increase that, if harnessed, can deliver major competitive advantages.
But to take advantage of these powerful new many-core processors, most users will have to radically redesign their software, potentially needing completely new algorithms that can exploit massive parallelism.
New many-core processors represent one of the biggest advances in computing in recent history. They also indicate the direction of all future processor design - we cannot avoid this major paradigm shift into massive parallelism. All processors from all the major vendors will become many-core designs over the next few years. Whether this is many identical mainstream CPU cores or a heterogeneous mix of different kinds of core remains to be seen, but it is inevitable that there will be lots of cores in each processor, and importantly, to harness their performance, most software and algorithms will need redesigning.
There is significant competitive advantage to be gained for those who can embrace and exploit this new, many-core technology, and considerable risk for any who are unable to adapt to a many-core approach. This report explains the background to these developments, presents several success stories, and describes a number of ways to get started with many-core technologies.
About the author
Simon McIntosh-Smith is head of the Microelectronics Research Group at the University of Bristol and chair of the Many-Core and Reconfigurable Supercomputing Conference (MRSC), Europe's largest conference dedicated to the use of massively parallel computer architectures. Prior to joining the university he spent fifteen years in industry where he designed massively parallel hardware and software at companies such as Inmos, STMicroelectronics and Pixelfusion, before co-founding ClearSpeed as Vice-President of Architecture and Applications. In 2006 ClearSpeed's many-core processors enabled the creation of one of the fastest and most energy-efficient supercomputers: TSUBAME at Tokyo Tech. He has given many invited talks on how massively parallel, heterogeneous processors are revolutionising high-performance computing, and has published numerous papers on how to exploit the speed of graphics processors for scientific applications. He holds eight patents in parallel hardware and software and sits on the steering and programme committees of most of the well-known international high-performance computing conferences.