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Europe’s exascale supercomputer prototype comes ARMed to the core

UK uber-chip designer, ARM, is at the heart of a European Commission-funded consortium of 12 technology companies and research institutions building an exascale supercomputer prototype.
The consortium, dubbed ExaNeSt, includes the UK’s University of Manchester, and is banking on ARM’s 64-bit four-cores to overcome key technical and architectural problems that need to be solved for exascale computing to become a reality. 
China and the US have already launched ambitious programmes to build high-performance supercomputers capable of at least one exaflop, the definition of an exascale system able to process vast amounts of data extremely quickly.
But, up to now, development has been in the doldrums, mainly due to the large amount of power required for such systems. 
That’s where ARMs energy-efficient cores could make all the difference, particularly when combined with liquid cooling and non-volatile flash memory that is integrated into the processors. The consortium believes that, with these measures, it is possible to overcome the energy, cooling and packaging problems of exascale computing designs.
Project partner and cooling vendor Iceotope, also UK-based, is providing the fully immersed cooling solution for the prototype. The  company recently showcased their cooling technology for ExaNest at SC15
ExaNeSt takes the approach of co-designing the hardware and software, enabling the prototype to run real-life evaluations. It’s overall goal is to develop and test new and emerging technologies in interconnects, storage, and cooling which in this case, applies to ARM-based machines.
It will take ten million processors working together to achieve Exascale – the equivalent of asking ten million individuals to solve, in a single second, a problem that would normally take one person 3 months (about ten million seconds). 
Reducing energy consumption, will mean that it’s possible to put the processors closer to each other and, with improved cooling, it will possible to accommodate more of them.
The system will use around 1,000 ARM cores and approximately 40 nodes that will be designed by the related ExaNode team based at the University of Manchester, which focuses on developing ARM-based HPC microserver designs.
Other project partners include the development and performance analysis tool developer Allinea, open source database consulting company MonetDB, the FORTH Institute of Computer Science in Greece, Italy's National Institute of Astrophysics and Institute of Nuclear Physics along with the Fraunhofer Institute of Industrial Mathematics in Germany.
The ExaNeSt partners anticipate a "straw man prototype" ready this year. A full prototype is expected to be ready by 2018.
While ARM in high performance computing is still emerging - in part, because 64-bit ARM processors have not been around for long  - Europe is pushing investment toward our native processor powerhouse.
The company is involved in a number of high profile schemes, including the Mont Blanc project at the Barcelona Supercomputer Center. There is potential  for ARM to tackle data-intensive workloads at CERN and work ongoing at the UK’s Hartree Centre using Lenovo ARM machines. Efforts are also underway to firm up the code base for future HPC applications running on the ARM architecture and ExaNest is not the only Horizon 2020 funded HPC project capitalising on ARMs world leading designs. 
Achieving the Holy Grail of Exascale computing will mean that unprecedented volumes of data can be moved, processed and managed, transforming our understanding of the world through advanced simulation and problem solving. It will allow greater insight into many areas of our lives including climate change, cosmology, drug design, energy safety, national security, material science, medicine and countless other scientific and engineering disciplines. 
Although we are still some time away from seeing powerful ARM-based machines topping the Top 500 list of the fastest supercomputers, momentum in Europe is building.
image: ExaNeSt
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